A flip-flop is a general data storage device used in a digital electronic circuit. The flip-flop can be a significant factor in designing a digital electronic circuit, since it is a clocked storage (or state) element used to design sequential and stable logic. The flip-flop can be used to store logic states, parameters, or digital control signals.
To realize a high-performance microprocessor, the flip-flop may be manufactured to operate at maximum logic clocking speed while reducing flip-flop setup/hold time and clock-to-output time. In addition, the flip-flops should have a short data response time while reducing data-to-clock time.
FIG. 1 is a circuit diagram of a conventional flip-flop 100. The flip-flop 100 includes a master terminal 110 and a slave terminal 120 that use tri-state buffers as switching elements. The master terminal 110 includes a first inverter 111 that receives a clock signal CK and outputs an inverted clock signal CKB, a second inverter 112 that receives the inverted clock signal CKB and outputs an internal clock signal CKI, a first tri-state buffer 113 that receives input data D in response to the internal clock signal CKI and the inverted clock signal CKB, and a first latch 114 that latches an output of the first tri-state buffer 113. The first latch 114 includes a third inverter 115 that receives the output of the first tri-state buffer 113, and a second tri-state buffer 116 that receives an output of the third inverter 115 and feeds back the received output to the third inverter 115 in response to the inverted clock signal CKB and the internal clock signal CKI.
The slave terminal 120 includes a third tri-state buffer 121 that receives an output of the first latch 114 in response to the inverted clock signal CKB and the internal clock signal CKI, a second latch 122 that latches an output of the third tri-state buffer 121, and a fourth inverter 123 that receives the output of the third tri-state buffer 121 and outputs an output signal Q. The second latch 122 includes a fifth inverter 124 that receives the output of the third tri-state buffer 121, and a fourth tri-state buffer 125 that receives an output of the fifth inverter 124 and feeds back the received output to the fifth inverter 124 to latch the output in response to the internal clock signal CKI and the inverted clock signal CKB.
FIG. 2 is a circuit diagram of a tri-state buffer, such as the tri-state buffers 113, 116, 121, and 125. Referring to FIG. 2, the tri-state buffer generates an output signal Y by inverting an input signal A in response to a first enable signal CKP and a second enable signal CKN. The tri-state buffer includes first and second PMOS transistors 201 and 202 and first and second NMOS transistors 203 and 204, which are connected in series between a supply voltage VDD and a ground voltage VSS. The input signal A is input to the gates of the first PMOS transistor 201 and the second NMOS transistor 204, the first enable signal CKP is input to the gate of the second PMOS transistor 202, and the second enable signal CKN is input to the gate of the first NMOS transistor 203. The logic levels of first enable signal CKP and the second enable signal CKN are different from each other (i.e., out of phase with one another), like the inverted clock signal CKB and the internal clock signal CKI illustrated in FIG. 1.
The flip-flop 100 stores the input data D in the master terminal 110 in response to the clock signal CK that goes to logic low, and outputs the data D stored in the master terminal 110 as the output signal Q to be output from the slave terminal 120 in response to the clock signal CK that goes to logic high. In this case, the tri-state buffers 113, 116, 121, and 125 of the flip-flop 100 are selectively enabled in response to the inverted clock signal CKB and the internal clock signal CKI. When the clock signal CK is input to the master terminal 110, the inverted clock signal CKB and the internal clock signal CKI are output from the first and second inverters 111 and 112, respectively. Accordingly, a delay in the operations of the first and second inverters 111 and 112 results can provide a delay in generation of the inverted clock signal CKB and the internal clock signal CKI. A delay in the generation of the inverted cock signal CKB and the internal clock signal CKI may reduce the operating speed of the flip-flop 100, which may affect the operating speed of the flip-flop 100.